The present application relates generally to the manufacture of semiconductor devices, and more specifically to the formation of air-gaps for electrical isolation and minimization of parasitic capacitance and inductive coupling within advanced FinFET nodes, such as between adjacent metal contacts and between metal contacts and transistor gates.
Conventional methods for forming contact metallization use successive etch and deposition steps to first form contact vias within an interlayer dielectric. The contact vias are then filled with a conductive material. However, the robustness and reproducibility of such a process is being challenged by decreasing device dimensions where, for example, patterning limitations at contact-to-contact spacings of less than 50 nm and contact-to-gate spacings of less than 20 nm at a 7 nm node can result in high leakage currents and electrical shorts, due at least in part to insufficient dielectric isolation between adjacent conductive structures and residual conductive material that bridges the gap between conductors. While an additional recess etch of the metallization material(s) may be used to remove surface residues, such additional processing disadvantageously adds additional manufacturing steps to the process.